The present invention relates to a method of manufacturing a semiconductor device, which can be used suitably to a method of manufacturing a semiconductor device having a non-volatile memory.
As electrically programmable and erasable non-volatile semiconductor memory devices, EEPROM (Electrically Erasable and Programmable Read Only Memory) have been employed generally. Such memory devices typically represented by flash memories and used generally at present have a conductive floating gate electrode surrounded by an oxide film or a trapping insulation film below a gate electrode of a MISFET, use the state of charges accumulated in the floating gate or the charge trapping insulation film as memory information, and read out the same as a threshold value of the transistor. This charge trapping insulation film is an insulation film capable of accumulating charges therein and includes, for example, a silicon nitride film. By injection and release of charges into and from the charge region, the threshold value of the MISFET is shifted to operate the same as a memory device. The flash memory includes a split gate cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. Such a memory uses a silicon nitride film as a charge accumulation region and has various advantages, for example, that it is excellent in the reliability of data holding compared with a conductive floating gate film due to discrete charge accumulation. In addition, owing to the excellent reliability of data holding, the thickness of the oxide film over and below the silicon nitride film can be reduced, making it possible to decrease the voltage for write and erase operations.
Japanese Patent Laid-Open No. 2003-243619 describes a technique relating to a non-volatile semiconductor memory device. Further, Japanese Patent Laid-Open No. 2010-10716 describes a technique relating to a dummy pattern in a semiconductor device having a step of planarizing the surface by using a CMP method. Further, Japanese Patent Laid-Open No. 2012-69837 describes a technique relating to a semiconductor device having a CMP step.